CONTROL DATA MODEL 160-A
March 1, 1961
CONTROL DATA CORPORATION MODEL 160-A COMPUTER,
The Control Data Model 160-A Computer is a highly flexible, multi-purpose, stored program data processor and converter. It employs high speed (2-1/2 megacycle clock frequency) transistor amplifier circuits, diode logic, and the fastest magnetic core matrix memory in its price class. Word construction is 12 binary digits, parallel throughout, programmable to multiple-precision and to alpha-numeric and binary-coded decimal.
Memory size is 8192 12-bit words with a storage cycle time of 6.4 microseconds. Additional memory modules of 8,192 12-bit words are available. The maximum memory size is 32,768 12-bit words. The standard instruction list comprises 91 instructions.
A general purpose input channel and output channel system is provided f o r attaching a variety of input-output devices. Input and output transmissions are either a single 6-bit, 7-bit or 8-bit character, or a 12-bit word. Standard input-output is by punched paper tape high-speed read and punch units. Optionally, other input - output devices, such as on-line typewriters, magnetic tape handlers, punched card units, digital communication units, analog-to-digital converters, or other similar equipments may be added.
Operation of the Model 160-A is sequenced by an internally stored program. This program, as well as the data being processed, is contained in the high-speed, random-access storage. An instruction is a 12-bit word comprising a 6-bit function code, F, and a 6-bit code extension and/or execution address, E. Program modifications are accomplished and operands are manipulated by direct, relative, or indirect addressing through the use of E. The average instruction execution time is 15 microseconds.
The Model 160-A is constructed in a standard-size office desk. Operating requirements are 1000 watts of 110-volt, 60 cycle power, and a normal room-temperature environment.
SUMMARY OF CHARACTERISTICS
Type of machine Digital, stored program Mode of operation Parallel Word Length 12 bits Memory 8,192 12-bit words expandable to 16,384, 24,576, 32,768 12-bit words. Type of instruction Single address Address features Direct, indirect and relative addressing Instruction Word 12-bit word (six-bit function code, F; six-bit execution address, E). Input-output Cedar punched paper tape reader ( 350 characters per second, six, seven or eight bits per character). Teletype high-speed paper tape punch (110 characters per second.). Instruction Repertoire 91 instructions for arithmetic and manipulative operations Type of Arithmetic Binary; one's complement
DESCRIPTION OF REGISTERS
The Control Data Model 160 - A Computer contains three operational registers, A, Z and P. These registers are referred to implicitly in the individual program steps. They are indicated on the control panel.
In addition to the operational registers, there are three transient registers, B, F and S. These registers are important only to the internal operation of the machine and are not indicated on the control panel.
There is also the Buffer Entrance Register, Buffer Exit Register and Buffer Input-Output Register.
As an aid to gaining a general familiarity with the Model 160-A, the registers, both operational and transient, are described below. A block diagram of the Model 160-A is shown in Figure 1.
A Register (12 bits). The A register is the principal arithmetic register. For most arithmetic operations, A operates as a 12-bit subtractive accumulator. The arithmetic operations of addition and subtraction are performed modulus 212 minus one. The quantity zero is represented by all zeros.
Z Register (12 bits). The Z register performs a variety of functions. It serves as a buffer register for storage. In this capacity, it receives the word read out of storage and holds the word to be written into storage. For addition and subtraction operations, it is the content of Z which is added to or subtracted from the content of A.
P Register (12 bits). The P register is the program control register. Its content is the address of the current instruction. At the beginning of each instruction, the content of P is increased by one to provide the address of the instruction or a jump address is entered in P if a jump is called for.
B Register (12 bits). The B register is an auxiliary arithmetic register. The results of arithmetic operations are first formed in B and then transmitted to the A, Z or S registers.
S Register (12 bits). The S register functions as the storage address register. Prior to any storage reference, the address word is entered in S. The content of S is then used to select the storage location involved in the reference.
F Register (6 bits). The F register holds the upper six bits of an instruction. word or a modified version of same, that is, the function code throughout the execution of the instruction. The execution of an instruction is under the control of the quantity in F. Figure 1. Block Diagram of the Control Data Model 160-A Computer
X000 to X110 Register (12 bits). Buffer Entrance Register. This register holds the address of the current memory location being referred to by the buffering operation.
X200 to X310 Register (12 Bits), Buffer Exit Register. This register holds a number one greater than the desired exit address.
X400 to X510 Register (12 Bits), Buffer Input-Output Register. This register contains the information in the process of being buffered in or out of the computer via the buffer channel.
Figure 1. Block Diagram of teh Control Data Model 160-A Computer
ADDRESSING MODESThe Control Data Model 160-A has facilities for addressing according to five execution address modes:
Direct Address (d) Indirect Address (i) Relative Address Forward (f) Relative Address Backward (b) No Address (n)
The Model 160-A repertoire contains 9 1 instructions. The various execution address modes for which E is used give the necessary flexibility with only a six-bit address.
In the direct addressing mode (d-mode), the address refers to a 12-bit operand in one of the first 64 words of storage.
Indirect addressing (i) provides for operand references and jump addresses. In the case of an instruction employing indirect addressing, E refers first to one of the first 64 storage locations, and then the contents of this address are read out and used as the address of the operand or as the jump address.
Relative addressing provides for operand addresses and jump addresses that are in the immediate vicinity of the storage location containing the current instruction. In relative addressing forward (f), the E portion is added to the current contents o f program control register P. The new value is then used to obtain the operand from, or to jump to, one of the 63 addresses forward of the address holding the instruction that is being executed. For relative addressing backward (b), the operand or jump address is obtained by subtracting E from the current contents of P. Thus the operated or jump address is one of the 63 immediately preceding the address of the current instruction. An exception is the Indirect Jump (f) in which the jump address is read from the address found when the contents of P are added to E.
In the no-address mode (n), the E portion of t h e instruction is not used as an address; instead, it is used as a six-bit operand. This operand is automatically extended to 12 bits, with t h e upper six bits being zeros. This feature permits the performance of arithmetic and logical operations with a six-bit quantity contained in the instruction, and thus eliminates the need for entering many constants into memory.
Instruction Repertoire of Instructions Common to 160 and 160-A
0000 Fault 40 Store (d) 01 Fixed Shift (n) 41 (i) 02 Logical product (n) 42 (f) 03 Logical Sum (n) 43 (b) 04 Load (n) 44 Shift replace (d) 05 Load complement (n) 45 (i) 06 Add (n) 46 (f) 07 Subtract (n) 47 (b) 10 Logical product (d) 50 Replace add (d) 11 (i) 51 (i) 12 (f) 52 (f) 13 (b) 53 (b) 14 Logical sum (d) 54 Replace add one (d) 15 (i) 55 (i) 16 (f) 56 (f) 17 (b) 57 (b) 20 Load (d) 60 Zero jump (f) 21 (i) 61 Non-zero jump (f) 22 (f) 62 Positive jump (f) 23 (b) 63 Negative jump (f) 24 Load complement (d) 64 Zero jump (b) 25 (i) 65 Non-Zero jump (b) 26 (f) 66 Positive jump (b) 27 (b) 67 Negative jump (b) 30 Add (d) 70 Indirect jump (d) 31 (i) 71 Indirect jump (f) 32 (f) 72 Input (f) 33 (b) 73 Output (f) 34 Subtract (d) 74 Output (n) 35 (i) 75 External function (f) 36 (f) 7600 Input to A 37 (b) 7777 Stop
Additional Instructions for the 160-A Computer
OO1X Shift relative (memory reference control to Bank X) 002X Shift indirect (memory reference control to Bank X) 003X Shift relative and indirect (memory reference control to Bank X) 004X Shift direct (memory reference control to Bank X) 005X Shift relative and direct (memory reference control to Bank X) 006X Shift indirect and direct (memory reference control to Bank X) 007X Shift relative, indirect and direct (memory reference control to Bank X) 0100 Initiate Buffer clear 0101 (P) to A 0104 Clear buffer control 0105 Transfer (A) to buffer entrance register 0106 Transfer (A) to buffer exit register 0107 Transfer (buffer entrance register) to A 014X Shift buffer memory reference control to Bank X 015X Store(P) 7100 Return Jump 7200 Initiate input buffer or sense jump B 7300 Initiate output buffer or sense jump B 7600 Input to A 7601 to
Half write indirect 7677 Output from A 7701 Key controlled stop (1) 7702 Key controlled stop (2) 7704 Key controlled stop (3) 7710 Key controlled jump (1) 7720 Key controlled jump (2) 7740 Key controlled jump (3)
DESCRIPTION OF INSTRUCTIONS COMMON TO 160 AND 160-A
Shift A. Left end around 1 Binary Bit Positions
Shift A, Left end around 3 Binary Bit Positions
Multiply contents of A by octal 12 (decimal 10).
LOGICAL PRODUCT (02, 10, 11, 12, 13)
Hold bits of the A register where there are ones in the operand; clear all other bits.
LOGICAL SUM (03, 14, 15, 16, 17)
Complement bits of the A register where there are ones in n the operand
LOAD (04, 20, 21, 22, 23)
Enter the operand into the A register
LOAD COMPLEMENT (05, 24, 25, 26, 27)
Enter the complement of the operand into the A register.
ADD (06, 30, 31, 32, 33)
Add the operand to the A register contents modulus 212 minus one.
SUBTRACT (07, 34, 35, 36, 37)
Subtract the operand from the A register contents modulus 212 minus one.
STORE (40, 41, 42, 43)
Replace the operand with the contents of the A register.
FIXED SHIFT (01)
The instruction 0110 shifts the contents of A three places (left circular). The instruction 0101 shifts the contents of A one place (left circular). The instruction 0112 then multiplies A by octal 12 (decimal 10).
SHIFT REPLACE (44, 45, 46, 47)
Add the operand to itself modulus 212 minus one. Then replace the operand and the contents of the A register with the result.
REPLACE ADD (50, 51, 52, 53)
Add the operand to the A register contents modulus 212 minus one. Then replace the operand and the contents of the A register with the result.
REPLACE ADD ONE (54, 55, 56, 57)
Add one to the operand modulus 212 minus one. Then replace the operand and the contents of the A register with the result.
ZERO JUMP (60, 64)
If the A register contains all zeros, add (or subtract) E to (or from) the program address. This causes the program to jump ahead (or back) by E.
If the A register does not contain all zeros, continue with the current program sequence.
NON-ZERO JUMP (61, 65)
If the A register does not contain all zeros, add (or subtract) E to (or from) the program address. This causes the program to jump ahead (or back) by E.
If the A register contains all zeros, continue with the current program sequence:
POSITIVE JUMP (62, 66)
If the A register is positive, add (or subtract) E to (or from) the program address. This causes the program to j u m p ahead (or back) by E.
If the A register is negative, continue with the current program sequence.
NEGATIVE JUMP (63, 67)
If the A register is negative, add (or subtract) E to (or from) the program address. This causes the program to jump ahead (or back) by E.
If the A register is positive, continue with the current program sequence.
INDIRECT JUMP (70)
Terminate the current program sequence and begin a new sequence at the address given by the content of address E.
INDIRECT JUMP (71)
Terminate the current program sequence and begin a new pro- gram sequence at the address specified by the content of the memory location E positions forward. E is added to P and a memory reference is made to that address to get the j u m p address which then replaces the current address in P.
Read a block (of one or more units) of input information to a storage input area. The starting address of the area is specified by the content of the storage location E positions forward of the input instruction. The terminating address of the area is specified by the content of the storage location immediately following the input instruction. Information is stored in successive storage locations beginning at the starting address and up to, but not including, the location specified by the terminating address.
The next instruction executed is in the second location following the input instruction. The input is terminated upon filling the input area, or upon receipt of an external disconnect from the input equipment.
A block of one or more output words is sent to an output device from the storage output area. The starting address of the area is specified by the content of the storage location E positions forward of the output instruction. The terminating address of the area is specified by the content of the storage location immediately following the output instruction. Information is obtained from successive storage locations beginning at the starting address and up to, but not including, the location specified by the terminating address. The next instruction executed is in the second location following the output instruction.
Enter the lower six bits of the instruction (E) in the output channel with zeros in the upper six bits and select the External Output Ready Line.
EXTERNAL FUNCTION (75)
Obtain the 12-bit operand E positions forward, enter it in the output register and select the External Function Ready Line.
INPUT TO A (7600)
12 bit input to A
STOP (0000, 7700, 7777)
Stop computation and wait for operator intervention.
INSTRUCTION EXECUTION TIMES
The execution times of the Model 160-A instructions are generally a direct function of the number of storage references required to execute the instruction. The instructions fall into five groups as follows:
One-storage-reference instructions (6. 4 microseconds)
Instructions 00, 01, 02, 03, 04, 05, 06, 07, 60, 61, 62, 63, 64, 65, 66, 67, 74, 77
Two-storage-reference instructions (12. 8 microseconds)
Instructions 10, 12, 13, 14, 16, 17, 20, 22, 23, 24, 26, 27, 30, 32, 33, 34, 36, 37, 70, 71, 75, 76
Three-storage-reference instructions (19. 2 microseconds)
Instructions 11, 15, 21, 25, 31, 35, 40, 42, 43, 44, 46, 47, 50, 52, 53, 54, 56, 57
Four-storage-reference instructions (25. 6 microseconds)
Instructions 41, 45, 51, 55
Instructions 72 and 73
These two instructions each require two storage references plus two storage references for each transmission of a data word. (12. 8 + 12. 8n microseconds where n is the number of words transmitted.)
The normal memory size is 8,192 12-bit words. This memory is physically contained in the computer desk-size cabinet. For additional capacity a memory cabinet is connected to the 160-A Computer. The cabinet contains memory modules of 8,192 12-bit words minimum and a maximum of three modules or 24,576 12-bit words. The maximum memory size is therefore 32,768 12-bit words using the three additional modules and the normal memory of 8,192 words.
The internal program will automatically switch from one memory bank to another depending on the addressing mode. The switching can also be accomplished by instructions which specifically assign and/or select the reference for a particular bank of memory.
NORMAL INPUT-OUTPUT SECTION
There are five instructions concerned with input-output operations. Instruction 72 is used to receive input quantities. Output data are sent by instructions 73 and 74. External function codes for directing the operation of the input-output equipment are sent by instruction 75. Instruction 7600 provides a 12-bit input to A and 7677, a 12-bit output from A.
Communication with external equipment is accomplished b y first executing instruction 75. The operand obtained by instruction 75 is the external function code. This code selects the particular equipment and specifies the mode in which it is to operate. This code is sent to the equipment via the output channel. As desired, the main program may now execute one of the instructions in the group 72, 73, 74, 7600 or 7677, to exchange data with the activated equipment. Only one input or one output equipment is active at a given time on the regular input-output channel.
The 72 and 73 instructions initiate a sequence of transmissions that are accomplished in the following manner. The address designated by the instruction (E addresses forward) is placed in the A register. The address in A is used for storing t h e input word or for reading a word for output.
After each transmission the address in A is advanced by one and compared with the content of the address immediately following the 72 or 73 instruction. If the comparison shows inequality, another transmission of a data word is initiated. If the comparison shows equality, the program continues with the instruction at the second address following the 72 or 73 instruction.
The 74 instruction initiates a single output operation with the six-bit quantity E being placed in the output channel.
BUFFER INPUT-OUTPUT SECTION
The input-output buffer register provides temporary storage for a 12 - bit word between computer memory and selected external devices. The buffer control contains a 12-bit entrance register and a 12-bit exit register which must be preset by the program. The entrance register contains the address of the memory location for the input or output word being transferred at any time during a buffered input-output operation. This register is s advanced by one each time a word is transferred. The exit register contains the input or output terminating address plus one. The contents of t h this s register is constantly compared with that of the entrance register and when comparison detects identity, the buffered input-output operation ceases.
Since these three registers exist and operate independently of the other computer registers, the computer is free to run its main program while the buffer is waiting for the slower external devices. While the buffer is in operation at the end of each memory reference cycle, the input-output control circuitry determines whether or not a word is ready to be buffered. If it is ready, the program is momentarily halted while the input or output word is processed after which the program is free to resume.
The computer periodically senses the input / output channels for the receipt of an interrupt. When an interrupt is detected, the program will jump to an interrupt sequence in memory. The interrupt sequence includes the instructions necessary to return to the main program at the proper time.
An interrupt is not recognized during a non-buffered input/output operation.
Equipments provided as an integral part of the basic computer for input and output are a Cedar 350 paper tape reader and a Teletype Model BRPE - 11 paper tape punch.
The Cedar paper tape reader can be used with either six-bit, seven-bit or eight-bit characters. Punched paper tape is read at a rate of 350 characters per second.
The Teletype Model BRPE-11 paper tape punch also can be used with either six-bit, seven-bit or eight-bit characters. Characters are punched at a rate of 110 per second.
Magnetic tape units employing Ampex Model FR-400 or TM-2 tape handlers may be added as optional equipment. Tapes produced b y these units are interchangeable with tapes from the Control Data Model 1607 Magnetic Tape System as well as tapes prepared by IBM 727 magnetic tape units. Information is written on and read from tape in six-bit or twelve-bit characters with appropriate parity checking procedures as part of the control associated with the individual tape unit. Tape running speed is 15,000 characters per second using the FR-400 and 30,000 characters per second using the TM-2.
A card read/punch unit may be connected to the Model 160-A by means of a card control unit containing the necessary assembly/ disassembly, buffer, translation and control circuitry. Data are read/punched a row at a time and transmitted to or from the Model 160-A in 12-bit words.
Other optional input-output equipment can be connected to the Model 160-A by suitable buffer units. For example, the Model 160-A may be connected to a Teletype line for on-line operation by means of a buffer which provides for assembling and level-changing.
The Control Panel includes a projection display as Arabic numerals (octal) of the translated contents of the A, Z and P registers. Pushbuttons are provided for manual entry of information into these registers.
All switches and indicators necessary to operate the Control Data Model 160-A are provided at this location. The four major sequences which accomplish the execution of an instruction are displayed on one display module along with various internal conditions. The RUN-STEP lever switch provides for performing a program a full speed (RUN position) or one sequence at a time (STEP position). The LOAD-CLEAR switch provides for loading from paper tape in the LOAD position and master clearing in the CLEAR position. The ENTER-SWEEP switch provides for entering information into storage from the Z register, and for reading information from storage and displaying it in Z (SWEEP). Maintenance checks o n the storage section are performed by the ENTER-SWEEP switch and the TEST switch. The key controlled stop and key controlled jump switches are located immediately under the A register.
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