1. System Description
Introduction	1-1
Systems Characteristics Summary	1-3
System Characteristics	1-4
Central Processor Characteristics	1-4
Peripheral and Control Processor Characteristics	1-5
Central Memory Characteristics	1-6
Display Console Characteristics	1-7
Systems Options	1-8
.
2. Central Memory
Organization	2-1
Address Format	2-1
Central Memory Access	2-1
Memory Protection	2-2
.
3. Central Processor
Organization	3-1
Central Processor Programming	3-4
Functional Units	3-5
Instruction Formats	3-5
Operating Registers	3-6
Exchange Jump	3-9
Exit Mode	3-11
Floating Point Arithmetic	3-15
Fixed Point Arithmetic	3-21
Description of Central Processor Instructions	3-22
Program Stop and No Operation	3-23
Increment	3-24
Fixed Point Arithmetic	3-28
Logical	3-29
Shift	3-32
Floating Point Arithmetic	3-37
Branch	3-43
Extended Core Storage Communication	3-46
.
4. Peripheral and Control Processors
Organization	4-1
Peripheral Processor Programming	4-6
Instruction Formats	4-6
Address Modes	4-6
Registers	4-8
Description of Peripheral Processor Instructions	4-9
No Operation	4-10
Data Transmission	4-11
Arithmetic	4-13
Shift	4-16
Logical	4-16
Replace	4-19
Branch	4-22
Central Processor and Central Memory	4-24
Input / Output	4-27
Access to Central Memory	4-32
Input and Output	4-35
Real- Time Clock	4-39
.
5. System Interrupt
Introduction	5-1
Hardware Provisions for Interrupt	5-1
Exchange Jump	5-1
Channel and Equipment Status	5-1
Exit Mode	5-2
.
6. Manual Control
Introduction	6-1
Dead Start	6-1
Load Mode	6-1
Sweep Mode	6-2
Dump Mode	6-2
Console	6- 4
Keyboard Input	6-4
Display	6-4

The CONTROL DATA* 6400, 6500, and 6600 Computer Systems are three large-scale, solid-state, general-purpose digital computing systems. The advanced design techniques incorporated in these systems provide for extremely fast solutions to data processing, scientific, and control center problems, as well as multiprocessing, time-sharing, and management information applications.

System Characteristics

• Large-scale, general-purpose computer system
• 11 independent computers; 12 in the Dual Processor 6500 system
  1 Central Processor (60-bit); 2 Central Processors in the 6500 system
  • 10 Peripheral and Control Processors (12-bit)
  Central Memory (60-bit)
  Display console and keyboard
• System communicates with a variety of external equipment
  • Disk files
  • Magnetic tapes
  • Card equipment
  • Printers
• Central Memory common to the system computers
• Maximum Central Memory storage capability 131, 072 words (60-bit)
  Major Cycle = 1000 ns (nanoseconds)
  Minor Cycle = 100 ns
  Memory organized in 32 banks of 4096 words
  Multiphase

  Central Processor instructions

  Arithmetic, logical, indexing, branch

  Peripheral and Control Processor instructions Add/Subtract, logical, input/output, access to Central Processor and Central Memory

  Each Peripheral and Control Processor has 12-bit 4096-word memory

  Solid-state system

  Transistor logic

Central Processor Characteristics

• 10 arithmetic and logical units

  Add	Shift
  Multiply	Branch
  Multiply	Boolean
  Divide	Increment
  Long add	Increment

• 24 operating registers for functional units
  8 operand (60-bit)
  8 address (18-bit)
  8 increment (18-bit)

  8 transistor registers (60-bit) hold 32 instructions (15-bit) or 16 instructions (30-bit) or a combination of the two for servicing functional units.

6400 and 6500

• Unified arithmetic section, operating in sequential manner (one per processor in 6500)
• 24 operating registers (one set per processor in 6500)
  8 operand (60-bit)
  8 address (18-bit)
  8 increment (18-bit)

  Instruction Buffer register (60-bit)

Common Central Processor Characteristics

• Floating point arithmetic
  Single and double precision
  Optional rounding and normalizing

  Format

  Integer coefficient - 48 bits

  Biased exponent - 11 bits (210)

  Coefficient sign - 1 bit

  Fixed point arithmetic (subset of floating point arithmetic)

  Full 60-bit add/subtract

  Controlled and started by Peripheral and Control Processors

  Addresses in Central Memory relative

Peripheral and Control Processor Characteristics

Central Memory Characteristics

Display Console Characteristics

• Two display tubes
• Modes
  character
  dot

  Character size

  Large - 16 characters/line

  Medium - 32 characters/line

  Small - 64 characters /line

  Characters

  26 alphabetic

  10 numeric

  11 special

The foregoing summary of characteristics assumed a 6400, 6500, or 6600 system with 10 Peripheral and Control Processors, a Central Processor (except for the 6500 system with its two identical Central Processors), and Central Memory with 131, 072 words (60-bit) of magnetic core storage.

Options listed below are available within each system unless otherwise noted.

• Central Memory with 131, 072 words (60-bit) of magnetic core storage.
• Central Memory with 65, 536 words (60-bit) of magnetic core storage. (This is the minimum Central Memory size available for the 6500 Computer System. )
• Central Memory with 32, 768 words (60-bit) of magnetic core storage.
• Extended Core Storage (Refer to ECS Reference Manual) available in the following sizes:
  125,952 words (60-bit)
  251,904 words (60-bit)
  503,808 words (60-bit)
  1,007,616 words (60-bit)
  2,015,232 words (60-bit)

  Extended Core Storage Controller: couples up to 2, 015, 232 words of Extended Core Storage from one to four 6400, 6500, or 6600 central computers) or Augmented I/O Buffer and Control unit(s) in any combination.

  Augmented I/O Buffer and Control: includes 16, 384 words (60-bit) of magnetic core storage and 10 Peripheral and Control Processors with storage.

  Central Processor Monitor Facility (Central and Monitor Exchange Jump instructions):Refer to the publications for Standard Options 10103 and 10104.

Central Memory is organized into 32K, 65K, or 131K words (60-bit) in 8, 16, or 32 banks of 4096 words each. The banks are logically independent, and consecutive addresses go to different banks. Banks may be phased into operation at minor cycle intervals, resulting in very high Central Memory operating speed. The Central Memory address and data control mechanisms permit a word to move to or from Central Memory every minor cycle.

The location of each word in Central Memory is identified by an assigned number (address), which consists of 18 bits. Address formats are shown below for 8-bank(32K), 16-bank (65K), and 32-bank (131K) systems. Within the address format, the bank portion specifies one of 8, 16, or 32 banks; the 12-bit address defines one of 4096 separate locations within the specified bank. Addresses written or compiled in the conventional manner reference consecutive banks and hence make most efficient use of the bank phasing feature.

1. FL is the number of 60-bit words comprising the program, not an address.
2. To avoid possible "artificial" range faults, instructions should not be stored near the upper limit address of the Field Length. For example, using absolute address [(RA + FL) - 1] for an instruction produces a range fault when the (look-ahead) Read Next Instruction occurs to (RA + FL). Data should always be stored in addresses near or approaching absolute location (RA + FL), rather than instructions.

The Central Processor is an extremely high-speed arithmetic processor which communicates only with Central Memory. It consists (functionally) of an arithmetic unit and a control unit. The arithmetic unit contains all logic necessary to execute the arithmetic, manipulative and logical operations. The control unit directs the arithmetic operations and provides the interface between the arithmetic unit and Central Memory. It also performs instruction fetching, address preparation, memory protection, and data fetching and storing.

The Central Processor is isolated from the Peripheral and Control Processors and is thus free to carry on high-speed computation unencumbered by input/output requirements.

The organization of the Central Processor in the 6400 system differs from the 6600 Central Processor in two important respects. The 6500 system has two Central Processors; each similar to the 6400 Central Processor. Central Processor differences are tabulated in Table 3-1.

Eight 60-bit registers are provided to hold instructions (6600), thereby limiting the number of memory reads for repetitive instructions, especially in inner loops. Multiple banks of Central Memory are also provided to minimize memory reference time. References to different banks of memory may be handled without wait.

Speed of operation in a conventional computer is also limited by the serial manner in which instructions are executed; instructions are executed sequentially in time with little or no concurrency.

In the 6600 Computer System, this delay is minimized by providing 10 arithmetic (functional) units and a reservation control. Unrelated instructions are executed simultaneously, provided no conflicts exist in the arithmetic units.

Central Processor program instructions are stored in Central Memory. A 60-bit memory location may hold 60 data bits, four 15-bit instructions, two 30-bit instructions or a combination of 15 or 30-bit instructions. Figure 3-1 shows all instruction combinations in a 60-bit word and the two instruction word formats.

The Central Processor reads 60-bit words from Central Memory and stores them in an instruction stack which is capable of holding up to eight 60-bit words.

Instruction Formats

In the 6600, it is permissible to pack the upper-order 15 bits (fmij portion) of a 30-bit instruction in the lowerorder 15-bit portion of an instruction word. When this 30- bit instruction is executed, the lower-order 15-bits of K are taken from the upper-order 15 bits of the instruction word. In the 6400 and 6500, any 30-bit instruction with its fmij portion packed in the lower-order 15 bits of an instruction word will be executed as a STOP instruction.

Operating Registers In order to provide a compact symbolic language, the 24 operating registers are identified by letters and numbers:

The A0 and X0 registers are independent and have no connection with Central Memory. They may be used for scratch pad or intermediate results. Note the special use of A0 and X0 when executing Extended Core Storage communication instructions.

The B registers have no connection with Central Memory. The BO register is fixed to provide a constant zero (18-bit) which is useful for various tests against zero, providing an unconditional jump modifier, etc. In general, the n registers provide means for program indexing. For example, B4 may store the number of times a program loop has been traversed, thereby providing a terminal condition for a program exit.

An Exchange Jump instruction from a Peripheral and Control Processor enters initial values in the operating registers to start Central Processor operation. Subsequent address modification instructions executed in the increment functional units provide the addresses required to fetch and store data.

Program Address
An 18-bit P register serves as a program address counter and holds the address for each program step. P is advanced to the next program step in the following ways:

1. P is advanced by one when all instructions in a 60-bit word have been extracted and sent to the instruction registers.

2. P is set to the address specified by a Go To . . . (branch) instruction. If the instruction is a Return Jump, (P) + 1 is stored before the branch to allow a return to the sequence after the branch.

3. P is set to the address specified in the Exchange Jump package.

Typically, the Reference Address (RA) for any program is left cleared to all zeros. When an error exit is taken, the Central Processor records at RA the exit condition (upper 2 octal digits only) and the Program Address at exit time (refer to the format below).

NOTE
The Exit condition(s) recorded at RA comprises all the Exit conditions detected since the last Exchange Jump, regardless of whether they were selected. Thus, com- binations of error Exit conditions (03, 05, 06 or 07) can appear at RA:

1. When at least one Exit condition was selected and the selected condition plus another condition occur- red since the last Exchange Jump, or

2. When more than one Exit condition was selected and each occurred in the same minor cycle.

Format
Floating point arithmetic takes advantage of the ability to express a number with the general expression kBⁿ where:

The base number is constant (2) for binary-coded quantities and is not included in the general format. The 60-bit floating-point format is shown below. The binary point is considered to be to the right of the coefficient, thereby providing a 48-bit integer coefficient, the equivalent of about 14 decimal digits. The sign of the coefficient is carried in the highest order bit of the packed word. Negative numbers are represented in one's complement notation.

The 11-bit exponent carries a bias of 2¹⁰ (2000₈) when packed in the floating point word (biased exponent sometimes referred to as characteristic). The bias is removed when the word is unpacked for computation and restored when a word is packed into floating format. Table 3-4 lists (in decimal and octal notation) the complete range of permissible exponents and the octal form of the corresponding positive and negative floating point words.

Normalizing and Rounding
Normalizing a floating point quantity shifts the coefficient left until the most significant bit is in bit 47. Sign bits are entered in the low-order bits of the coefficient as it is normalized. Each shift decreases the exponent by one.

A round bit is added (optionally) to the coefficient during an arithmetic process and has the effect of increasing the absolute value of the operand or result by one-half the value of the least significant bit. Normalizing and rounding are not automatic during pack or unpack operations so that operands and results may not be normalized.

A result the exponent of which is less than the lower limit of octal 0000 (underflow case) is treated as a zero quantity. This quantity is packed with a zero exponent and zero coefficient. No exit is provided for underflow. A result with an exponent of octal 0000 and a coefficient which is not zero is a non-zero quantity and is packed with a zero exponent and the non-zero coefficient.

Note 1. Overflow of Upper Sum: Overflow cannot occur unless one operand is infinite. In this case the eresult is as indicated. If a one-place Right Shift occurs when the larger operand exponent is equal to +1776₈, a correct result with exponent +1777₈ is generated.

Note 2. Underflow of Exponent During Normalization: The final (B_j) are the same as if underflow had not occurred. In particular, if the initial coefficient is zero, (B_j) are equal to 60₈.

Fixed point addition and subtraction of 60-bit numbers are handled in the Long Add Unit (6600). Negative numbers are represented in one's complement notation, and overflows are ignored. The sign bit is in the high-order bit position (bit 59) and the binary point is at the right of the low-order bit position (bit 0).

The Increment Units provide an 18-bit fixed point add and subtract facility. Negative numbers are represented in one's complement notation and overflows are ignored. The sign bit is in the high-order bit position (bit 17), and the binary point is at the right of the low-order bit position (bit 0). The Increment Units allow program indexing through the full range of Central Memory addresses.

Fixed point integer addition and subtraction are possible in the Floating Add Unit providing the exponents of both operands are zero and no overflow occurs. The unit performs the one's complement addition (or subtraction) in the upper half of a 98-bit accumulator. If overflow occurs, the unit shifts the result one place right and adds one to the exponent, thereby producing a floating point quantity. Thus, care must be used in performing fixed point arithmetic in the Floating Add Unit.

Fixed point integer multiplication is handled in the multiply functional units as a subset operation of the unrounded Floating Multiply (40, 42) instructions. The multiply is double precision (96 bits) and allows separate recovery of upper and lower products. The multiply requires thatboth of the integer operands be converted (by program) to floating format to provide biased exponents. This insures that results are not sensed as underflow conditions. The bias is removed when the result is unpacked.

This section describes the Central Processor instructions. Instruction grouping follows a somewhat pedagogical approach (i.e., simple to complex) and does not necessarily relate instructions to the functional units (6600 system) which execute them. Central Processor instructions as related to functional units are tabulated in Appendix B, Instruction Execution Times.

Program Stop and No Operation

00

PS

.

Program Stop

(30 Bits)

46

NO

.

No operation (Pass)

(15 Bits)

Increment

50	SAi	Aj + K	Set Ai to Aj + K	(30 Bits)
51	SAi	Bj + K	Set Ai to Bj + K	(30 Bits)
52	SAi	X j + K	Set Ai to X j + K	(30 Bits)

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18- bit result in address register i. Overflow, in itself, is ignored, but an address range fault may result from overflow in this set of instructions.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. Note that an immediate memory reference is performed to the address specified by the final content of address registers A1 - A7. The operand read from memory address specified by Al - A5 is sent to the corresponding operand register X1 - X5. When A6 or A7 is referenced, the operand from the corresponding X6 or X7 operand register is stored at the address specified by A6 or A7.

NOTE
If, in this category of instructions, the result placed in address register Ai is an address out of range, the following occurs: (Note that this action is independent of an Exit selection on Address Out of Range.) If i = 1-5: Operand register Xi is loaded with the contents of absolute address zero and the contents of memory location (Ai) are unchanged. If i = 6 or 7: Operand register Xi retains its original contents and the contents of memory location (Ai) are unchanged.

EXAMPLE:				Initial Quantities:
   50  SAi     Aj + K	i = 4	K = 2345678
       SA4     A6 + K	j = 6	A4 = 3211108
       SA4 = 4321008 +	2345678	A6 = 4321008
       SA4 = 6666678	X4 = 00.....008
                      Storage location 666667 = 7. . . 753421046008
                      Final Quantities:
                      A4 = 6666678
                      A6 = 4321008
                      X4 = 7. .. 753421046008

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word.

70	Six	Aj + K	Set Xi to Aj + K	(30 Bits)
71	SXi	Bj + K	Set Xi to Bj + K	(30 Bits)
72	SXi	Xj + K	Set Xi to Xj + K	(30 Bits)

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18-bit result into the lower 18 bits of operand register Xi. The sign of the result is extended to the upper 42 bits of operand register Xi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. EXAMPLE:

					Initial Quantities:
	73	SXi	Xj + Bk	i = 2	X2 = 0. . . 07453214028
		SX2	X3 + B1	j = 3, K = 1	X3 = 0_ . . 06522243108
		SX2 =	0. . . 06522243108 + 5112458   B1= 5112458
		SX2 =	7. . . 77777355558
					Final Quantities:
                              X2 = 7...77777355558
                              X3 = 0...06522243108
                              B1 =         5112458

Fixed Point Arithmetic

36

IXi

Xj +Xk

Integer sum of Xj and Xk to Xi

(15 Bits)

37

IXi

Xi - Xk

Integer difference of Xj and Xk to Xi

(15 Bits)

47

CXi

Xk

Count the number of "1's" in Xk to Xi

(15 Bits)