GE-625 / 635
Programming
Reference Manual
GE-625 / 635
Programming
Reference Manual
GE-625/635
PROGRAMMING
REFERENCE MANUAL
July 1964
Rev. January 1966
GENERAL 
ELECTRIC
COMPUTER DEPARTMENT
The GE-625/635 Programming Reference Manual is the basic document for programming the GE-625/635. It essentially describes programming-related GE-625/635 machine features, the instruction repertoire, and the symbolic machine language oriented Macro Assembler. The Assembler chapter and the examples in Chapter IV describe how the programmer may write Processor instructions using a symbolic notation.
The Programming Reference Manual is one of a set of user publications
for programming the GE-625/635 computer. The others of the set, together
with pertinent and necessary programming information contained in each,
are:
| PUBLICATION | PROGRAMMING INFORMATION |
|---|---|
| GE-625/635 FORTRAN IV
Reference Manual, CPB-1006 | FORTRAN IV language specifications, coding rules and restrictions,
and compiler informa-tion for the GE-625/635
|
| GE-625/635 COBOL
Reference Manual, CPB.-1007 | COBOL-61 Extended language specifications, coding rules and
restrictions and compiler information for the GE-625/635
|
| GE-625/635 File and Record Control Reference Manual, CPB-1003 (GE FRC) | Standard input/output coding by use of calling sequences to
software system input/output routines.
|
| GE-625/635 Comprehensive Operating Supervisor Reference Manual, CPB-1002 (GE COS) |
|
| GE-625/635 General Loader Reference Manual, CPB-1008, (GE LOAD) |
|
| GE-625/635 Sort/Merge Reference Manual, CPB-1005 |
|
| GE-625/ 635 Bulk Media Conversion Reference Manual, CFB-1096 | Description of deck preparation for bulk media conversion run |
This reference manual is addressed to programmers experienced with coding in the environment of a large-scale computer installation. It assumes some knowledge and experience in the use of address modification with indirection, hardware indicators, fault interrupts and recovery routines, macro operations, pseudo-operations, and other features normally encountered in a fast, large memory capacity computer with a very flexible instruction repertoire - -under control of a master executive program. It is also assumed that the programmer is familiar with the 2's complement number system as used in a sign-number machine.
Comments on this publication niay be addressed to Technical Publications,
Computer Department, General Electric Company, P. 0. Box 2961, Phoenix,
Arizona, 85002.
 |
|
| Figure | Page | |
|---|---|---|
| II-1 | Block Diagram of Principal Processor Registers | |
| II-2 | Table of Faults | |
| II-3 | Ranges of Fixed-Point Numbers | |
| II-4 | Ranges of Floating-Point Numbers | |
| II-5A | Address Modification Flow Chart | |
| II-5B | Address Modification Flow Chart | |
| III-1 | GE-625/635 MacroAssembler coding Form |
|
The basic GE-625/635 computer system is made up of four principle hardware components:
The Memory module, unlike most computer systems which are processor-oriented, is the over-all system control agency. It serves as a passive coordinating component that provides interim information storage and general system communication control. The module comprises two major functional units: the System Controller and the Magnetic Core Storage Unit. The principle features of the module and the performing units are:
| FEATURE | FUNCTIONAL UNIT | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| System Controller (eight priority-linked channel cells plus an associated mask register) | ||||||||
|
The Processor module is composed of two principal functional units: the Program Control Unit and the Operations Unit. The chief features of the module and the performing units are:
|
The Input/Output Controller module is the coordinator of all input/output data transfers between the complement of peripheral subsystems and the Memory module. It is in fact a separate processor which, when provided with certain required information from the Comprehensive Operating Supervisor and the user program, works independently of the Processor module under control of its own permanently-wired program.
The major functional units of the Input Output Controller are (1) the Memory Interface, (2) the Buffer Storage, (3) the Micro-Program Generator, (4) the I-O Processor, and (5) the PUB* Interrupt Service. The main features of this module and the performing units are:
| FEATURE | FUNCTIONAL UNIT | ||||||
|---|---|---|---|---|---|---|---|
|
|
The primary objectives of the GE-635 software system are:
The attainment of these objectives is achieved by the General Comprehensive Operating Supervisor (GECOS) (the overall manager of the software system) through efficient use of the hardware features and the supervision of a multiprogramming environment (which is the normal operating mode of the GE-625/635). The significant features provided by the Operating Supervisor as related to the several primary objectives above are summarized in the list following. These features are implemented by the modules and submodules within the Comprehensive Operating Supervisor.
Although each user-programmer writes his job program as though he had exclusive use of the computer, he is in fact generating a program that will reside concurrently in memory with other user programs and will be executed in a time-shared manner; that is, any given program is processed until it is held up (usually because of the need for some input/output to be completed) at which time the next most urgent program is processed. Transfer between programs under multiprogram execution is performed by means of the hardware interrupt facility (in the System Controller) working with the Dispatcher routines in the Input/Output Supervisor. The ways by which a user program can be temporarily delayed in execution are:
| DELAY TYPE | REASON |
|---|---|
| Roadblock | Program cannot progress until all input/output requests have terminated |
| Relinquish | Program relinquishes control so that some other program may be executed |
| Forced Relinquish | Program was interrupted because a timer run-out occurred. |
Each time a program yields control to the Operating Supervisor by means of Roadblock, Relinquish or by Forced Relinquish listed above, the Supervisor has the opportunity to give control to another program in core which can make effective use of the Processor.
In giving such control, the Supervisor examines the following conditions:
Media conversions are of two basic types (1) bulk media conversion, whereby large volumes of data in a single format and for a single purpose are processed and, (2) system media con-version where low-volume sets of data--each with its own format and purpose--are processed.
Bulk media conversion is performed by a system routine which may be called into execution by use of a control card. Other control cards will direct the routine as to where to find the input and where to place the output.
On-line media conversions for both input and output are performed as a normal part of the multiprogramming environment of the GE-625/635, Normal job input is carried out by input media conversion, which reads card input from the card reader, scans the control cards for execution information, and records the job on the input queue located on the system drum.
System media conversions of program output data are automatically
performed by the Output Media Conversion routine executed in protected
memory. The programmer specifies that a particular output file be written
on the permanently assigned system output (SYSOUT) file by use of the
PRINT, PUNCH, or WTREC calling sequences described in the GE-635 File
and Record Control Reference Manual. Once on the SYSOUT file, the output
is converted to hard copy or punched cards by the Output Media Conversion
routine, concurrently with other user programs under execution in the
multiprogramming environment.
Centralized Input/Output
In the multiprogramming environment where several programs may concurrently request input/ output, a facility must be provided (1) for processing such multiple requests in terms of the efficient use of the entire peripheral complement and, (2) for maintaining continuous processing of the multiple programs in core storage. The Comprehensive Operating Supervisor module that performs these general functions is the Input/Output Supervisor.
The main functions of the Input/Output Supervisor are to initiate an input/output activity and to respond to the termination of an input/output activity. In addition, the Input/Output Super-visor provides the following functions:
When the Input/Output Supervisor receives a request to perform an input/output function, it looks at the communication cells and issues a connect instruction. If the particular channel is busy, the request is placed in a waiting queue. If the request queue is full or if the program indicated that it should be roadblocked until all input/output is complete, then control is given to another program residing in memory.
When the input/output operation terminates, control is given to the
Input/Output Supervisor to perform all necessary termination functions.
At this point, the request queue is examined and if any requests for
the channel are in queue, they will be executed.
Master/Slave Relationship
Each Processor has the capability of operating in the Slave Mode or in the Master Mode. Master Mode is established for exclusive use by the Operating Supervisor. When executing a user program. a Processor is in Slave Mode. The prime reason for the Master Mode of operation is to protect the Operating Supervisor and user programs as well from modification by other user programs. This feature is vital in the multiprogramming environment and is closely tied in with memory protection, accounting determinations, multiprogram interrupt management, intermodule communications control, and input/output operations. Each of these functions is implemented by a Processor instruction that requires the Master Mode. These are listed below.
All instructions available to the Processor in Slave Mode are available in Master Mode. The following instructions can be executed only when the Processor is in Master Mode.
The last of these instructions, Connect Input/Output Channel, is the
beginning of every peripheral operation. Thus, all peripheral operations
are reserved for execution in Master Mode, and in particular by the
Input/Output Supervisor within the Comprehensive Operating Supervisor.
Master Mode Entry
Although Master Mode operation by the Processor is a primary safeguard
for executive routines and user programs in memory, the applications
programmer can force the Processor into this mode but only for accessing
routines that are part of the Operating Supervisor. This is done by use
of the Master Mode Entry (MME) instruction and one of the system-symbol
operands listed in Appendix E and described fully in the General
Comprehensive Operating Supervisor Manual. Any other use of MME causes
an abort of the user program. Thus, through the MME instruction, the
programmer can communicate with modules of the Operating Supervisor to
exchange any necessary information for the execution of his program.
Mass Storage Orientation
"Compute overhead" time is reduced and multiprogramming is enhanced through the use of an external drum (mass) storage unit. The drum (and optionally a disc storage device) enables optimized accessing of system routines and performs data transfers at higher rates than other external storage media.
The drum and or disc is used primarily for the following purposes:
The software system is further described as file oriented because
(1) the Comprehensive Opera-ting Supervisor assigns peripheral devices
to an activity and (2) it manages all assigned periph-erals during input
or output operations so that the programmer never deals directly with
input/ output subsystems or devices. The programmer references all
peripherals by use of file code designators, two alphanumeric characters,
that are referenced in two ways: (1) on file control cards used by the
Allocator in the Operating Supervisor to specify those files needed to
execute
the activity and, (2) in communicating to the File and Record Control
program or to the Input/Output Supervisor. The file code designators and
their assigned peripheral devices are maintained in the Peripheral
Assignment Table (PAT) used by the Input/Output Supervisor for
peripheral identification.
Software Reference Documentation
The following manuals and documents contain detailed descriptions of items mentioned in this chapter.
|
Since the Control Unit runs independently of the Memory module, a single Processor can be connected to memories with different cycle times. The Processor is designed to eliminate adverse interaction when memories with different cycle times are employed.
The Operations Unit performs all arithmetic and logical operations as directed by the Control Unit. The Operations Unit contains most of the registers available to a user program. This unit performs such functions as:
To permit separation of control and object programs with corresponding protection of control programs from undebugged object programs, two modes of operation, Master and Slave, are provided in the Processor. Control programs will run in the Master Mode, and object programs will run in the Slave Mode. Programs running in Master Mode have access to the entire memory, may initiate peripheral and internal control functions, and do not have base address relocation applied. Programs running in Slave Mode have access to a limited portion of the memory, cannot generate peripheral control functions, and have the Base Address Register added to all relative memory addresses of the object program.
Master Mode operation is the state in which the Processor:
The Processor is in the Master Mode when any of the following exists:
Slave Mode operation is the state in which the Processor:
The Processor is in the Slave Mode when the Master Mode Indicator is in
the slave condition or when the Transfer and Set Slave (TSS) instruction
is being executed. (See page II- 11.)
Operation Overlapping
Instruction words are fetched in pairs and sequentially transferred to the Control Unit of the Processor where the instructions are directed to the primary and secondary instruction registers of the instruction decoder. If required, address modification is then performed using the first of the two instructions.
As soon as this is accomplished, the operand specified by the first instruction is requested from memory while the Control Unit concurrently performs any address modification required by the second of the instruction pair.
When the operand called for by the first instruction is obtained, the
Control Unit transfers the operand to the Operations Unit, thus initiating
the specified operation to be carried out. While this operation is being
carried out by the Operations Unit, the operand specified by the second
instruction is requested by the Control Unit. As soon as the second operand
is received and the Operations Unit has finished with the first operand,
the Control Unit signals the Oprations Unit to carry out the second operation.
Finally, while the second operation is being carried out, the next instruction
pair is requested from memory.
Address Range Protection
Any object program address to be used in a memory access request while the Processor is in the Slave Mode is checked, just prior to the fetch, for being within the address range allocated by the Comprehensive Operating Supervisor (GECOS) to the program for this execution. This address range protection is commonly referred to as memory protection.
For the purpose of memory protection, the 18-bit Processor Base Address Register is loaded by GECOS with an address range in bit positions 9-16. The check takes place only in the Slave Mode. It consists of subtracting bit positions 0-7 of the program address from this address range, using the boundary adder. When the result is zero or negative, then the program address is out of range; and a Memory Fault Trap occurs. (Refer to page 11-14.)
More specifically, the checking is actually based on nine bits, namely the Base Address Register positions 9-17 and the bit positions 0-8 of the program address. This permits address range allocation to job programs in multiples of 512 words. Because of a software requirement, bits 8 and 17 of the Base Address Register have been wired in such a way that they contain zeros permanently and cannot be altered by the LBAR instruction. Thus, memory allocation and protection is performed in multiples of 1024 words.
In the Master Mode no checking takes place; thus, any memory location (in
those Memory modules that are connected to this Processor) can be accessed.
Execution of Interrupts
When an execute interrupt request present signal is received from a Memory module system controller for which the Processor is the control Processor, the Processor carries out the interrupt procedure as soon as an instruction from an odd memory location has been executed that:
The interrupt procedure consists of the following steps:
-------------+--------+-----------+---+------------------------- | 000 000 000 | Memory | Interrupt | 0 | Operation code, inhibit | | | No | Cell No. | | bit and tag fields | -------------+--------+-----------+---+------------------------- 0 8 9 11 12 16 17 18 35
The memory number is determined by the position of the address reassignment switches (A0 A1 A2 ) associated with the system controller causing the execute interrupt. The switches are three-position toggles having the positions 0, 1, and EITHER. A switch in the EITHER position is interpreted as a 0 in preparing the address for the instruction.
The cell number is determined by the highest priority unmasked interrupt cell (in the system controller) causing the execute interrupt.
Each of the two instructions from the memory location Y-pair may affect the Master Mode Indicator as follows:
The first of the two instructions from the memory location Y must not
alter the contents of the location of the second instruction, and must
not be an XED instruction. If the first of the two instructions alters
the contents of the Instruction Counter, then this transfer of control
is effective immediately; and the second of the two instructions is
not executed.
Interval Timer
The Processor contains a timer which provides a program interrupt at
the end of a variable interval. The timer is loaded by GECOS and can be
set to a maximum of approximately four minutes total elapsed time.
(See pages 11-7 and 11-13)
REGISTERS
The Processor block diagram (Figure lI-i) shows the program accessible registers as well as the major nonprogram accessible registers, adders, and switches. Only data and information paths are shown. The block diagram also shows the division between the Operations Unit and Control Unit.
The switches (rounded figures on the block diagram) control the flow of
information between the registers, adders, and the memory interface.
Program Accessible Registers
The following table shows the registers accessible to the program.
| Name | Mnemonic | Length |
|---|---|---|
| Accumulator Register | AQ | 72 bits |
| Eight Index Registers (n=O,. 3) | Xn | 18 bits each |
| Exponent Register | B | 8 bits |
| Base Address Register | BAR | 18 bits |
| Indicator Register | IR | 18 bits |
| Timer Register | TR | 24 bits |
| Instruction Counter | IC | 18 bits |
Program Nonaccessible Registers
The following listed registers are used in Processor operations but are not referenced in machine instructions.
| Mnemonic | Length |
|---|---|
| M | 72 bits |
| H | 72 bits |
| N | 72 bits |
| D | 8 bits |
| G | 8 bits |
| ADR | 18 bits |
| YE | 18 bits |
| YO | 18 bits |
| COE | 18 bits |
| COO | 18 bits |
The following table lists the Processor adders.
| Name | Length |
|---|---|
| S | 72 bits |
| YS | 18 bits |
| ES | 10 bits |
| BS | 9 bits |
| RS | 9 bits |
The indicators can be regarded as individual bit positions in an 18-bit half-word Indicator Register (IR).
An indicator is set to the ON or OFF state by certain events in the Processor, or by certain instructions. The ON state corresponds to a binary 1 in the respective bit position of the IR; the OFF state corresponds to a 0.
The description of each machine instruction on pages II-39 through II-137 includes a statement about (1) those indicators that may be affected by the instruction and (2) the condition under which a setting of the indicators to a specific state occurs. If the conditions stated are not satisfied, the status of this indicator remains unchanged.
The instruction set includes certain instruction which transfer data between the lower half of a storage location and the Indicator Register. The following table lists the indicators that have been implemented, their relation to the bit positions of the lower half of a memory location, and the instructions directly affecting indicators.
| Assigned | Bit Position | Indicator | Indicator Instructions | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Assigned | 18 | Zero |
|
The following descriptions of the individual indicators are limited to
general statements only.
Zero Indicator
The Zero Indicator is affected by instructions that change the contents
of a Processor register (A, Q, AQ, Xn, BAR, IR, TR) or adder, and by
comparison instructions.
The indicator is set ON when the new contents of the affected register
or adder contains all binary 0's; otherwise the indicator is set OFF.
Negative Indicator
The Negative Indicator is affected by instructions that change the contents of a Processor register (A, Q, AQ, Xn, BAR, IR, TR) or adder, and by comparison instructions.
The indicator is set ON when the new contents of bit position 0 of this
register or adder is a binary 1; otherwise it is set OFF.
Carry Indicator
The Carry Indicator is affected by left shifts, additions, subtractions, and comparisons.
The indicator is set ON when a carry is generated out of bit position
0; otherwise it is set OFF.
Overflow Indicator
The Overflow Indicator is affected by the arithmetic instructions,
but not by compare instructions and Add Logical (ADL(R)) or Subtract
Logical (SBL(R)) instructions
Exponent Overflow Indicator
The Exponent Overflow Indicator is affected by arithmetic operations with floating-point numbers or with the exponent register (E).
The indicator is set ON when the exponent of the result is larger than +127 which is the upper limit of the exponent range.
Since it is not automatically set to OFF otherwise, the Exponent
Overflow Indicator reports any exponent overflow that has happened since
it was last set OFF by certain instructions
(LDI, RET, and
Transfer on Exponent Overflow (TEO)).
Exponent Underflow Indicator
The Exponent Underflow Indicator is affected by arithmetic operations with floating-point numbers, or with the exponent register (E).
The indicator is set ON when the exponent of the result is smaller than -128 which is the lower limit of the exponent range.
Since it is not automatically set to OFF otherwise, the Exponent
Underfiow Indicator reports any exponent underflow that has happened
since it was last set OFF by certain instructions
(LDI, RET, and
Transfer on Exponent Underflow (TEU)).
Overflow Mask Indicator
The Overflow Mask Indicator can be set ON or OFF only by the instructions LDI and RET.
When the Overflow Mask Indicator is ON, then the setting ON of the Overflow Indicator, Exponent Overflow Indicator, or Exponent Underflow Indicator does not cause an Overflow Fault Trap to occur. When the Overflow Mask Indicator is OFF, such a trap will occur.
Clearing of the Overflow Mask Indicator to the unmask state does not
generate a fault from a previously set Overflow Indicator,
Exponent Overflow Indicator, or Exponent Underfiow Indicator.
The status of the Overflow Mask Indicator does not affect the setting,
testing, or storing of the Overflow Indicator, Exponent Overflow Indicator,
or Exponent Underflow Indicator.
Tally Runout Indicator
The Tally Runout Indicator is affected by the Indirect Then Tally (IT) address modification type (all designators except Indirect and Fault) and by the Repeat, Repeat Double, and Repeat Link instructions (RPT, RPD, and RPL).
The termination of a Repeat instruction because a specified termination condition is met sets the Tally Runout Indicator to OFF.
The termination of a Repeat instruction because the tally count reaches
0 (and for RPL because of a 0 link address) sets the Tally Runout Indicator
to ON; the same is true for tally equal to 0 in some of the IT address
modifications.
Parity Error Indicator
The Parity Error Indicator is set to ON when a parity error is detected during the access of one or both words of Y-pair from memory.
It may be set to OFF by the LDI or
RET instruction.
Parity Mask Indicator
The Parity Mask Indicator can be set to ON or OFF only by the instructions
LDI and RET.
When the Parity Mask Indicator is ON, the setting of the Parity Error
Indicator does not cause a Parity Error Fault Trap to occur. When the
Parity Mask Indicator is OFF, such a trap will occur.
Clearing of the Parity Mask Indicator to the unmasked state does not
generate a fault from a previously set Parity Error Indicator. The status
of the Parity Mask Indicator does not affect the setting, testing, or
storing of the Parity Error Indicator.
Master Mode Indicator
The Master Mode Indicator can be changed only by an instruction. For a description of how the indicator can be changed, refer to the following instruction descriptions:
| Instruction | Reference |
|---|---|
| Master Mode Entry (MVIE) | Page II-123 |
| Return (RET) | Page II-116 |
| Derail (DRL) | Page II-124 |
| Transfer and Set Slave (TSS) | Page II-115 |
When the Master Mode Indicator is ON, the Processor is in the Master
mode; however, the converse is not necessarily true. (See the MME and
DRL descriptions.)
FAULT TRAPS
Trapping Procedure
Sixteen types of faults and other events each have a fault trap assigned. Some of these events have nothing to do with actual faults; they are included here because they are treated the same as faults.
The fault trap procedure is similar to the interrupt procedure (page II-4) except that the effective address is defined differently. The fault trap procedure consists of the following steps:
-------+------------+------------+--- | ZEROS | Constant | Code | 0 | -------+------------+------------+--- 0 5 6 12 13 16 17
Each of the two instructions from the memory location Y-pair may affect the Master Mode Indicator as follows: If this instruction results in an actual transfer of control and is not the Transfer and Set Slave instruction (TSS), then ON: if this instruction is either the Return instruction (RET) with bit 28 equal to 0 or the TSS instruction, then OFF.
The first of the two instructions from the memory location Y must not
alter the contents of the location of the second instruction, and must not
be an Execute Double instruction (XED). If the first of the two
instructions alters the contents of the Instruction Counter, then this
transfer of control is effective immediately; and the second of the two
instructions is not executedú
Fault Categories
There are four general categories of faults:
If a parity error occurs on any instruction for which the C(Y) are taken from a location (this includes "to storage" instructions, ASA, ANSA, etc., the Processor operation is completed with the faulty operand before entering the fault routine.
The generation of this fault is inhibited when the Parity Mask Indicator is in the mask state. Subsequent clearing of the Parity Mask to the unmasked state will not generate this fault from a previously set Parity Error Indicator. The Parity Mask does not effect the setting, testing, or storing of the Parity Indicator.
The above two are dependent on other switch positions on the Processor control panel.
The 16 faults are organized into five groups to establish priority for the recognition of a specific fault when faults occur in more than one group. Group I has highest priority.
Only one fault within a priority is allowed to be active at any one
time. In the event that two or more faults occur concurrently, only the
fault which occurs first through normal program sequence is permitted.
Fault Recognition
Faults in Groups I and II cause the operations in the Processor to abort unconditionally.
Faults in Groups III and IV cause the operations in the Processor to abort conditionally upon the completion of the operation presently being executed.
Faults in Group V are recognized under the same conditions that
Program Interrupts are recognized. (See page II-4.) Faults in Group V
have priority over Program Interrupts and are also subject to being
inhibited form recognition by use of the inhibit bit in the instruction
word.
Instruction Counter (IC)
Upon recognition of a fault, the contents of the Instruction Counter (IC) are shown in the Table of Faults below.
| Fault No. | Fault Name | Group (Priority) | IC Contents |
|---|---|---|---|
| 1100 | Startup | I | N+0,1, or 2 |
| 1111 | Execute | I | N+0,1, or 2 |
| 1011 | Operation Not Completed | II | N+0,1, or 2 |
| 0111 | Lockup | II | N+0,1, or 2 |
| 1110 | Divide Check | III | N (Note 4) |
| 1101 | Overflow | III | N |
| 1001 | Parity | IV | N (Note 2) |
| 0101 | Command | IV | N+1 |
| 0001 | Memory | IV | N+1 (Note 4) |
| 0010 | Master Mode Entry | IV | N (Note 4) |
| 0110 | Derail | IV | N (Note 4) |
| 0011 | Fault Tag | IV | N (Note 4) |
| 1010 | Illegal Op Code | IV | N |
| 1000 | Connect | V | N |
| 0100 | Timer Runout | V | N |
| 0000 | Shut Down | V | N |
Notes:
Figure II-2. Table of Faults
THE NUMBER SYSTEM
The binary system of notation is used throughout the GE-635 information processing system.
Many of the instructions, mainly additions, subtractions, and comparisons, can be used in two ways: either operands and results are regarded as signed binary numbers in the 2's complement form (the "arithmetic" case), or they are regarded as unsigned, positive binary numbers (the "logic" case). The Zero and the Negative Indicators facilitate the general interpretation of the results in the arithmetic case; the Zero and the Carry Indicators, in the logic case. The instruction set contains instruction types "Add Logic" and "Subtract Logic" which particularly facilitate arithmetic of the logic type with half-word, single-word, and double-word precision.
Subtractions are carried out internally by adding the 2's complement of the subtrahend.* It is a characteristic feature of the 2's complement representation that a "no borrow" condition in the case of true subtraction corresponds to a "carry" condition in the case of addition of the 2's complement, and vice versa.
A statement on the assumed location of the binary point has
significance only for multiplications and divisions. These two operations
are implemented for integer arithmetic as well as for fractional
arithmetic with numbers in 2's complement form, "integer" meaning that
the position of the binary point may be assumed to the right of the
least-significant bit position (that is, to the right of bit position
35 or 71, depending on the precision of the respective number) and
"fractional" meaning that the position of the binary point may be
assumed to the left of the most-significant bit position (that is,
between the bit positions 0 and 1).
REPRESENTATION OF INFORMATION
The Processor is fundamentally organized to deal with 36-bit groupings
of information. Special features are also included for ease in
manipulating 6-bit groups, 18-bit groups, and 72-bit, double-precision
groups. These bit groupings are used by the hardware and software to
represent a variety of forms of information.
Position Numbering
The numbering of bit positions, character positions, words, etc., increases in the direction of conventional reading and writing: from the most- to the least-significant digit of a number, and from left to right in conventional alphanumeric text.
Graphical presentations in this manual show registers and data with
position numbers increasing from left to right.
The Machine Word
The machine word consists of 36 bits arranged as follows:
0 17 | 18 35 ------------------+----------------- | One Machine Word | ------------------+----------------- Upper Half word | Lower Half word
Data transfers between the Processor and memory are word orientated: 36 bits are transferred at a time for single-precision data and two successive 36-bit word transfers for double-precision data. When words are transferred to a Magnetic Core Storage Unit, this unit adds a parity bit to each 36-bit word before storing it. When words are requested from a Magnetic Core Storage Unit, this unit verifies the parity bit read from the store and removes it from the word transferred prior to sending each word to the Processor.
The Processor has many built-in features for transferring and processing pairs of words, transferring a pair of words to or from memory, a pair of memory locations is accessed; the addresses are an even and the next-higher odd number.
0 35 | 36 72 ------------------+----------------- | A Pair of Machine Words | ------------------+----------------- Even Address | Odd Address
In addressing such pairs of machine locations in an instruction that is intended for handling pairs of machine words, either of the two addresses may be used as the effective address (Y). Thus,
If Y is even, the pair of locations (Y, Y+1) is accessed. If Y is odd, the pair of locations (Y-1, Y) is accessed. The term "Y-pair" is used for each such pair of addresses.
Alphanumeric data are represented by six-bit or nine-bit characters. A machine word contains either six or four characters:
Character positions within a word :
------+------+------+------+------+------ | 0 | 1 | 2 | 3 | 4 | 5 | six-bit ------+------+------+------+------+------ 0 5 6 11 12 17 18 23 24 29 30 35 ---------+---------+---------+--------- | 0 | 1 | 2 | 3 | nine-bit ---------+---------+---------+--------- 0 8 9 17 18 26 27 35
-----+-----+-----+-----+-----+----- | 0 | 1 | 3 | 4 | 4 | 5 | six-bit -----+-----+-----+-----+-----+----- -----+-----+-----+-----+-----+-----+-----+-----+----- | 0 | 1 | 3 | 4 | 4 | 5 | 6 | 7 | 8 | nine-bit -----+-----+-----+-----+-----+-----+-----+-----+-----
The character set used is the Computer Department Standard Character
Set, which is readily convertible to and from the ASCII character set.
Binary Fixed-Point Numbers
The instruction set comprises instructions for binary fixed-point arithmetic with half-word, single-word, and double-word precision.
PRECISION REPRESENTATION
--------- --------------
------------------ - - - - - - - - -
Upper Half | | |
------------------ - - - - - - - - -
0 17
Half-word
- - - - - - - - - -----------------
Lower Half | | |
- - - - - - - - - -----------------
18 35
----------------------------------
Single-word | |
----------------------------------
0 35
---------------------------------- ----------------------------------
Double-word | | |
---------------------------------- ----------------------------------
0 35 36 72
Even Address Odd Address
Instructions can be divided into two groups according to the way in which the operand is interpreted: the "logic" group and the "algebraic" group.
For the "logic" group, operands and results are regarded as unsigned, positive binary numbers. In the case of addition and subtraction, the occurrence of any overflow is reflected by the carry out of the most-significant (leftmost) bit position:
| 1. | Addition | -- If the carry out of the leftmost bit position equals 1, then the result is above the range. |
| 2. | Subtraction | -- If the carry out of the leftmost bit position equals 0, then the result is below the range. |
In the case of comparisons, the Zero and Carry Indicators show the relation.
For the "algebraic" group, operands and results are regarded as signed, binary numbers, the leftmost bit being used as a sign bit, (a 0 being plus and 1 minus). When the sign is positive all the bits represent the absolute value of the number; and when the sign is negative, they represent the 2's complement of the absolute value of the number.
In the case of addition and subtraction the occurrence of an overflow is reflected by the carries into and out of the leftmost bit position (the sign position). If the carry into the leftmost bit position does not equal the carry out of that position then overflow has occurred. If overflow has been detected and if the sign bit equals 0, the resultant is below range; if with overflow, the sign bit equals 1, the resultant is above range.
An explicit statement about the assumed location of the binary point is necessary only for multiplication and division; for addition, subtraction, and comparison the binary points are "lined up."
In the GE-625/635 Processor, multiplication and division are implemented in two forms for 2's complement numbers: integer and fractional.
In integer arithmetic, the location of the binary point is assumed to the right of the least-significant bit position, that is, depending on the precision, to the right of bit position 35 or 71. The general representation of a fixed-point integer is then:
-an2n +an-12n-1 +an-22n-2 ... +a121 +a020
where an is the sign bit.
In fractional arithmetic, the location of the binary point is assumed to the left of the most-significant bit position, that is, to the left of bit position 1. The general representation of a fixed-point fraction is then:
-a020 +a12-1 +a22-2 ... +an-12-(n-1) +an2-n
The number ranges for the various cases of precision, interpretation, and arithmetic are listed in Figure II-3.
| Interpretation | Arithmetic | Precision | ||
|---|---|---|---|---|
| Half-Word (Xn, Y0..17) | Single-Word (A,Q,Y) | Double-Word (AQ, Y-pair) | ||
| Algebraic | Integral | -217 <= N <= (217 - 1) | -235 <= X <= (235-1) | -271 <= N <= (271-1) |
| Fractional | -1 <= N <= (1-2-17) | -1 <= N <= (1-2-35) | -1 <= N <= (1-2-71) | |
| Logic | Integral | 0 <= N <= (218)-1) | 0 <= N <= (236)-1) | 0 <= N <= (272)-1) |
| Fractional | 0 <= N <= (1-2-18)-1) | 0 <= N <= (1-2-36)-1) | 0 <= N <= (1-2-72)-1) | |
Figure II-3. Ranges of Fixed Point Numbers
Binary Floating-Point Numbers
The instruction set contains instructions for binary flaoting-point arithmetic with numbers of single-word and double-word precision. The upper 8 bits represent the integral exponent E in the 2's complement form, and the lower 28 or 64 bits represent the fractional mantissa M in 2's complement form. The notation for a floating point number Z is:
Z(2) = M(2) * 2E(2)
Single-Word precision:
0 1 7 8 9 35 ---+------------+---+-------------------------------------- | s | | s | | ---+------------+---+-------------------------------------- | E | M |
Double-Word precision:
0 1 7 8 9 71 ---+------------+---+----------------------------------------------------- | s | | s | | ---+------------+---+----------------------------------------------------- | E | M |
Where S = Sign bit
Before doing floating point additions or subtractions, the Processor aligns the number which has the smaller positive exponent. To maintain accuracy, the lowset sermissible exponint of -128 together with the mantissa equal to 0.000....0 has beed defined as the machine representation of the number zero (which has no unique floating-point representation). Whenever a floating point operation yeilds a resultant untruntcated machine mantissa equal to zero (71 bits plus sign because of extended precision), the exponent is automatically set to -128.
The general representation of the exponent for single and double precision is:
-e727+e626+ . . . +e121+e020
where e7 is the sign.
The general representations of the single- and double-precision mantissa are:
where m0 is the sign in both cases.
Normalized Floating-Point Numbers
For normalized floating point numbers, the binary point is placed at the left of the most-significant bit of the manitssa (to the right of the sign bit). Numbers are normalized by shifting the mantissa (and correspondingly adjusting the exponent) until no leading zeros are present in the mantissa for positive numbers, or until no leading ones are present in the mantissa for negative numbers. Zeros fill in the vacated bit positions. With the exception of the number zero (represented as 0 * 2-128), all normalized floating point numbers will contain a binary 1 in the most-significant bit position for positive numbers and a bianry 0 in the most-significant bit position for negative numbers. Some examples are:
| Unnormalized positive number | (0|0001101) * 27 | |
| Same number normalized | (0|1101000) * 24 | |
| Unnormalized negative number | (1|11010111) * 2-4 | |
| Same number normalized | (1|01011100) * 2-6 |
The numberof ranges resulting from the various cases of precision, normalization, and sign are listed in the table following:
| Sign | Single Precision | Double Precision | |
|---|---|---|---|
| Normalized | Positive | 2-129 <= N <= (1-2-27) 2127 | 2-129 <= N <= (1-2-63) 2127 |
| Negative | -(1+2-26)2-129= N >= -2127 | -(1+2-62)2-129= N >= -2127 | |
| Unnormalized | Positive | 2-155 <= N <= (1-2-27) 2127 | 2-191 <= N <= (1-2-63) 2127 |
| Negative | -2-155 >= N >= -2127 | -2-191 >= N >= -2127 |
NOTE: The floating-point number zero is not included in the table.
Figure II-4. Ranges of Floating-Point Numbers
Decimal Numbers
The instruction set does not comprise instructions for decimal arithmetic. The represetation of decimal numbers in the machine therefore depends entirely on the programs used for performing the decimal arithmetic required.
The representation of te decimal digits as a subset of the character set
is shown in Appendix F.
Instructions
Machine instructions have the following general format:
---------------------------+------------+---+---+---+-------------- | y | op code | 0 | i | 0 | tag | ---------------------------+------------+---+---+---+-------------- 0 17 18 26 27 28 29 30 35
Where
The three repeat instructions, Repeat, Repeat Double, and Repeat Link (RPT, RPD, and RPL) use a different instruction format. (See pages II-125, II-127, and II-129.
Indirect words have the same general format as the instruction words;
however, the fields are used in a somewhat different way. (See page II-26
and following.)
ADDRESS TRANSLATION AND MODIFICATION
Address Translation
Any program address to be used in a memory access request while the Processor is in the Slave Mode is first translated into an actual address and then submitted to the memory.
The term "program address" is used for the following addresses:
For the purpose of address translation, the Processor Base Address Register contains a base address in bit positions 0-7. The translation takes place only in the Slave Mode of operation. It consists of adding this base address to bit positions 0-7 of the program address, using the Relocation Adder (RS).
In the Master Mode no address translation takes place. Any program address to be used in a memory access request while the Processor is in the Master Mode is used directly as an actual address and submitted to the memory without any translation.
Address translation is actually based on nine bits, namely the Base
Address Register positions 0-8 and the bit positions 0-8 of the program
address; this permits address relocation by multiples of 512 words.
Because of a software requirement, bit positions 8 and 17 of the Base
Address Register have been wired in such a way that they contain
0's permanently and cannot be altered by the Load Base Address Register
(LBAR) instruction, Thus, address relocation is performed in multiples of
1024.
Tag Field
Before the operation of an instruction is carried out, an address modification procedure generally takes place as directed by the tag field of the instruction and possibly of indirect words. Only the repeat mode instructions RPT, RPD, and RPL do not provide for an address modification. (See pages II-125, II-127, and II-129.
The tag field consists of two parts, tm and td that are located within the instruction word as follows:
30 31 32 35 ---+---+---+---+---+--- | | | ---+---+---+---+---+--- | tm | td |
Where
- tm
- specifies one of the four possible modification types: Register (R), Register then Indirect (RI), Indirect then Register (IR), and Indirect then Tally (IT)
- td
- specifies further the action for each modification type:
- In the case of tm = R, RI, or IR, td is called the register designator and generally specifies the register to be used in indexing.
- In the case of tm = IT, td is called the tally designator and specifies the tallying in detail.
The following table gives a general characterization of each of the four modification types.
| tm | Binary | Modification Type |
|---|---|---|
| R | 00 | Register Indexing according to td as register designator and termination of the address modification procedure. |
| RI | 01 | Register then Indirect Indexing according to td as register designator, then substitution and continuation of the modification procedure as directed by the Tag field of this indirect word. |
| IR | 11 | Indirect then Register Saving of td as final register designator, then substitution and continuation of the modification procedure as directed by the Tag field of this indirect word. |
| IT | 10 | Indirect then Tally Substitution, then use of this indirect word according to td as tally designator. |
Each of the three modification types R, RI, IR includes an indexing step which is further specified by the register designator td In most cases, td really specifies the register from which the index is obtained. However td may also specify a different action, namely that the effective address Y is to be used directly as operand and not as address of an operand (DU, DL), or that nothing takes place at all (N). Nevertheless td is called "register designator" in these cases.
| Register Designator | Action | ||
|---|---|---|---|
| Symbolic | Binary | ||
| N | 0000 | y | replaces Y |
| X1 | 1001 | y + C(Xn) | replaces Y |
| X2 | 1010 | ||
| . | . | ||
| X7 | 1111 | ||
| AU | 0001 | y + C(A)0..17 | replaces Y |
| AL | 0101 | y + C(A)18..35 | replaces Y |
| QU | 0010 | y + C(Q)0..17 | replaces Y |
| QL | 0110 | y + C(A)18..35 | replaces Y |
| IC | 0100 | y + C(IC) | replaces Y |
| DU | 0011 | y, 00...0 | is the operand |
| DL | 0111 | 00...0,y | is the operand |
The modification type IT consists of a substitution and the use of this indirect word as specified by the td of the instruction or previous indirect word as tally designator.
The format of the indirect word is:
------------------+------------+------ | y | Tally | Tag | ------------------+------------+------ 0 17 18 29 30 35
Where
y = address field Tally = tally field Tag = tag field
Depending upon the prior tally designator, the tag field is used in one of three ways:
...
The following table gives the possible tally designators under IT type modification.
| Tally Designator | Name | |
|---|---|---|
| Symbolic | Binary | |
| I | 1001 | Indirect only |
| DI | 1100 | Decrement Address, Increment Tally |
| AD | 1011 | Add Delta (from address field) |
| SD | 0100 | Subtract Delta (from address field) |
| ID | 1110 | Increment Address, Decrement Tally |
| DIC | 1101 | Decrement Address, Increment Tally, and Continue |
| IDC | 1111 | Increment Address, Decrement Tally, and Continue |
| CI | 1000 | Character form Indirect |
| SC | 1010 | Sequence Character |
| F | 0000 | Fault |
All possible types and sequences of address modification are shown on the following two flow charts.
| Modification Type | Flow Chart |
|---|---|
| R, IR, and RI address modification | Figure 11-5A |
| IT address modification | Figure II-5B |
See explanation of symbols and descriptions of modifications immediately following these figures.
Figure II-5A. Address Modification Flowchart
Explanation of Symbols Used on Flowcharts
| y, tm,td | is the original address, tag modifier, and tag designator, respectively. |
| Cf, Tally, Delta | is the value of the character field, tally field,and delta field of an indirect word. |
| 4 | should be read "replaces." |
| C(---) | should be read "the contents of ---." |
| Y | is the final effective address to be used in carrying out an instruction operation. |
| Yi | is the address of an indirect word which will be used for further modification. |
| Yii | is the address, obtained from another indirect word, of an indirect word which will be used for further modification. |
| (---) | represents quantities obtained from the contents of an indirect word. |
| ((---)) | represents quantities obtained from the contents of an indirect word which was obtained through another indirect word. |
| td* | is the register designator to be used as a final register modifier under IR modification. |
| Original | Most indirect words which are used under IT modification utilize the read-alter-rewrite (RAR) memory cycle. This RAR cycle must be completed before another indirect cycle can occur. The word original refers to the quantity contained in an indirect word before that quantity is incremented (during the alter part of the RAR cycle). Omission of the word original refers to the quantity after it is incremented or decremented during the alter portion of the RAR cycle. |
| End | indicates that the modification procedure for that instruction has terminated and the effective address Y, developed up to that point, is used to carry out the instruction operation. |
| 1 | The instruction word address field serves as the initial value of the tentative address y, and its tag field supplies the initial modifier tm as well as initial designator td | ||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | tm is one of the four modification types: R, RI, IR, or IT. | ||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | y modified by td replaces the former tentative address y. If td = DU or DL, DU or DL is ignored and the modification proceeds as if td = N. | ||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | The tentative address y, developed up to that point, becomes the address Yi. to be used in accessing an indirect word which will be used for further modification. Using Yi the indirect word is fetched. | ||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | The address and tag fields of the last indirect word replace the tentative address and the tag of the instruction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 |
The last designator t| 7 |
tm, of the indirect word, designates one of the four
modification types: R, RI, IR, or IT.
| 8 |
The address of the indirect word (y), modified by the final register
modifier td*, replaces the former tentative address.
| 9 |
The tentative indirect address (y), developed up to that point,
is used as the effective address Y for carrying out the instruction
operation.
| 10 |
The designator of the indirect word (td) replaces the final
register designator td*.
| 11 |
The tentative indirect address (y), developed up to that point becomes
the address Yii, to be used in accessing another indirect
word which will be used for further modification. Using Yii,
the indirect word is fetched.
| 12 |
The address (y), contained in the indirect word and modified by the
designator of the indirect word (td), replaces the
tentative indirect address (y).
| 13 |
y modified by td replaces the former tentative address y.
| 14 |
The tentative address y, developed up to that point, is used as the
effective address Y for carrying out the instruction's operation.
| 15 |
td is one of the nine tally designators: SC, CI, DIG, AD,
IDC, F, DI, I, or ID.
| 16 |
A value one less than or one greater than the value of the tally field
loaded from the indirect word becomes the new value of the tally field,
depending on the use of the AD or SD designator.
| 17 |
The Tally Runout Indicator is set to ON if the tally field equals zero
after incrementation or decrementation; the Indicator is set to
OFF if the tally field does not equal zero after incrementation
or decrementation.
| 18 |
A value one greater than the value of the character field loaded from
the indirect word becomes the new value of the character field.
| 19 |
If the value of the character field Cf equals six, the
character field is set to zero; and a value one greater than the value
of the address field loaded from the indirect word becomes the new value
of the address field.
| 20 |
During the rewrite portion of the read-alter-rewrite cycle used for
updating an indirect word, the updated fields -- (y), (Cf),
(Tally), (Delta), (tm), (td), where applicable --
are returned to storage in memory.
| 21 |
The original value of the address field (y), as loaded from the indirect
word before any incrementation or decrementation, becomes the
effective address Y which is used to carry out the instruction operation.
| 22 |
The original value of the character field Cf, as loaded from
the indirect word before any incrementation (or setting to zero),
is the value used in carrying out the instruction operation. (See note
at end of this listing.)
| 23 |
A value one less than the value of the address field loaded from the
indirect word becomes the new value of the address field.
| 24 |
A value one greater than the value of the tally field loaded from the
indirect word becomes the new value of the tally field.
| 25 |
Under IDC or DIG types of modification, the modifiers permitted within the
indirect are:
td = N
m
t = IR
td = N
m
t =RI
td = N
m
t = IT any
td
m
t = R effectively terminates the modification procedure while
m
t = RI, IR, or IT seeks at least an additional level of modification.
m
| 26 |
The original value of the address field (y), as loaded from the indirect
word before incrementation, becomes the address Yii to
be used in accessing the next indirect word which will be used for further
modification.
| 27 |
The address and tag fields of Yii replace the address and tag
fields of the original instruction, and modification proceeds as directed
by the new tag field.
| 28 |
Occurs when tm = IT and td = F, or when Fault tag
fault is initiated and no further indirect addressing occurs.
| 29 |
A value one greater than the value of the address field loaded from the
indirect word becomes the new value of the address field.
| 30 |
A value equal to the value of the address field (loaded from the indirect
word) plus or minus Delta (a constant also loaded from the indirect word)
replaces the value of the address field, The constant is positive for
the AD designator and negative for the SD designator.
| 31 |
The value of the character field Cf, after incrementation
(or setting to zero), is used in carrying out the instruction operation.
(See the note at the end of this listing.)
| 32 |
The original value of the address field and the tag field of the last
indirect word replace the tentative address and tag of the instruction.
| |
When the tally designator is CI or SC, the character field of the last indirect word is an octal number which specifies the character position of the memory location Y to be used in carrying out the instruction operation (the example uses a value of 3 in the character field).
....
For six-bit character operations in which the operand is taken from memory, the effective operand from memory is presented as a single word with the specified character justified to character position 5; positions 0-4 are presented as zero. For operations in which the resultant is placed in memory, character 5 of the resultant replaces the specified character in memory location Y; the remaining characters in memory location Y are not changed.
For nine-bit character operations in which the operand is taken from
memory, the effective operand from memory is presented as a single word
with the specified character justified to character position 3; positions
0-2 are presented as zero. For operations in which the resultant is
placed in memory, character 3 of the resultant replaces the specified
character in memory location Y; the remaining characters in memory
location Y are not changed.
CALCULATION OF INSTRUCTION EXECUTION TIMES
The instruction execution times (Appendix A) are based on fetching of instructions in pairs from memory, and in the case of overlap type instructions, also on overlap between the operation execution of the overlap type instruction and the fetching and address modification of the next instruction. (Overlap type instructions = multiplications; divisions; shifts; floating-point operations except "loads" and "stores".)
Certain operations prevent the fetching of instructions in pairs or the overlapping; accordingly, the following time adjustments should be made.
The instruction execution times of shift and floating-point operations are listed as "average times based on a number of five-shift steps. Note that a single-shift step may effect a shift by one, four, or sixteen positions. Actual times for these instructions may vary by up to + 0.8 microseconds. Where unnornialized operands are used in normalizing floating-point operations, worst-case conditions can add as much as 1.5 microseconds.
Address modifications do not require any time adjustments except in the following cases:
The GE-625/635 instruction set described under this heading is arranged by functional class, as listed in Appendix A. Appendix A together with Appendix B, which lists the instructions in alphabetical order by mnemonic, afford convenient page references to the instructions in this section, Appendix C presents the instruction mnemonics grouped by operation code.
For the description of the machine instructions that follow it is
assumed that the reader is familiar with the general structure of the
Processor, the representation of information, the data formats, and the
method of address modifications, as presented in the preceding paragraphs
of this chapter.
Format of Instruction Description
Each instruction in the repertoire is described in the following pages of this chapter. The descriptions are presented in the standardized format shown below.
| Mnemonic: | Name of the Instruction: | Op Code (octal) | |||
|
| |||||
| SUMMARY: | |||||
| MODIFICATIONS: | |||||
| INDICATORS: | (Indicators not listed are not affected) | ||||
|
| |||||
| NOTE: | |||||
This line has three headings that appear over boxes containing the following:
The following abbreviations and symbols will be used for the description of the machine operations.
Registers:
| A | - | Accumulator Register (36 bits) | |
| Q | - | Quotient Register (36 bits) | |
| AQ | - | Combined Accumulator-Quotient Register (72 bits) | |
| Xn | - | Index Register n (n = 0, 1,. . . , 7) (18 bits) | |
| E | - | Exponent Register (8 bits) | |
| EA | - | Combined Exponent-Accumulator Register (8 + 36 bits) | |
| EAQ | - | Combined Exponent-Accumulator-Quotient Register (8 + 72 bits) BAR = Base Address Register (18 bits) | |
| IC | - | Instruction Counter (18 bits) | |
| IR | - | Indicator Register (18 bits, 11 of which are used at this time) | |
| TR | - | Timer Register (24 bits) | |
| Z | - | Temporary Pseudo-result of a non-store comparative Operation. |
Effective Address and Memory Locations:
| Y | - | The effective address (18 bits) of the respective instruction. | |
| Y-pair | - | A symbol denoting that the effective address Y designates a pair of memory locations (72 bits) with successive addresses, the lower one being even. When the effective address is even, then it designates the pair (Y, Y+1), and when it is odd, then the pair (Y-1, Y). In any case the memory location with the lower (even) address contains the more significant part of a double-precision number or the first of a pair of instructions. |
Register Positions and Contents:
("R" standing for any of the registers listed above as well as for a memory location or a pair of memory locations.)
| Ri | = | the ith position of R | |
| Ri...j | = | the positions i through j of R | |
| C(R) | = | the contents of the full register R | |
| C(R)i | = | the contents of the ith position of R | |
| C(R)i...j | = | the contents of the positions i through j of R |
When the description of an instruction states a change only for a part of a register or memory location, then it is always understood that the part of the register or memory location which is not mentioned remains unchanged.
Other Symbols:
| =>i | = | replaces | |
| ::i | = | compare with | |
| ANDi | = | the Boolean connective AND (symbol A) | |
| ORi | = | OR = the Boolean connective OR (symbol V) | |
| R!= | = | the Boolean connective NON-EQUIVALENCE (or EXCLUSIVE OR) |
It is a characteristic feature of the GE-625/635 computer that an address translation takes place with each memory access when the Processor operates in the Slave Mode.
During the execution of a program, a base address is contained in the bit positions 0-7 of the Processor Base Address Register. With each memory access, this base address is added to bit positions 0-7 of the program address supplied by this program in order to generate the actual address used in accessing the memory. In this way, the address translation provides complete independence of the program address range from the actual address range that is used with a specific execution of this program.
Only when the Processor is in the Master Mode is the program address used directly as an actual address; in this case, program addresses generally refer to the Comprehensive Operating System which has allocated to it the actual address range beginning at zero.
The descriptions of the individual machine instructions in this chapter do not mention the address translation. It is understood here that an address translation has to be performed immediately prior to each memory access request (in the Slave Mode) regardless of whether:
No address translations take place for effective addresses which are
used either as operands directly or in other ways (for example, shifts).
Floating-Point Arithmetic
Numbers in floating-point representation are stored in memory as follows:
| Integer Exponent | Fractional Mantissa | |
|---|---|---|
| Single-word precision | C(Y)0...7 | C(Y)8...35 |
| Double-word precision | C(Y-pair)0...7 | C(Y-pair)8...71 |
When a floating-point number is held in the register EAQ, its mantissa length is allowed to increase to the full length of the register AQ.
....
In storing a floating-point number, a truncation of the mantissa takes
place. With single-word precision store Instructions, only
C(AQ)0-27 will be stored as mantissa, and with double-word
precision store instructions, only C(AQ)0-63.
DESCRIPTIONS OF THE MACHINE INSTRUCTIONS
| DATA MOVEMENT LOAD |
| Mnemonic: | Name of the Instruction: | Op Code (octal) | ||||
| ||||||
| SUMMARY: | C(Y) => C(A) | |||||
| MODIFICATIONS: | All | |||||
| INDICATORS: | (Indicators not listed are not affected) | |||||
| ||||||
| Mnemonic: | Name of the Instruction: | Op Code (octal) | ||||
| ||||||
| SUMMARY: | C(Y) => C(Q) | |||||
| MODIFICATIONS: | All | |||||
| INDICATORS: | (Indicators not listed are not affected) | |||||
| ||||||
| Mnemonic: | Name of the Instruction: | Op Code (octal) | |||
| |||||
| SUMMARY: | C(Y-pair) => C(AQ) | ||||
| MODIFICATIONS: | All exce | ||||