The Instruction-set Processor: Main-line computers
| Section 1 | . | Processors with One Address per Instruction |
| . | 4 | Preliminary Discussion of the Logical Design of an Electronic Computing Instrument" by Burks, Goldstien, & von Neumann |
| . | 5 | The DEC PDP-8 |
| . | 6 | The Whirlwind I Computer |
| . | 7 | Some Aspects of the Logical Design of a Control Computer, A Case Study |
| . | 8 | The UNIVAC System - Eckert, ... |
| Section 2 | . | Processors with General-register State |
| . | 9 | The design philosophy of Pegasus, a quantity-production computer |
| . | 10 | An 8-bit-character computer |
| Part 3 | . | The Instruction-set Processor Level: Variations in the Processor |
| Section 1 | . | Processors with Greater than One Address per instruction |
| . | 11 | The Pilot ACE |
| . | 12 | ZEBRA, a simple binary computer |
| . | 13 | UNIVAC Scientific (1103A) instruction logic |
| . | 14 | Instruction logic of the MIDAC |
| . | 15 | Instruction logic of the Soviet Strela (Arrow) |
| Section 2 | . | Processors constrained by a cyclic, primary memory |
| . | 16 | The LGP-30 and LGP-21 |
| . | 17 | IBM 650 Instruction Logic - John Carr |
| Section 3 | . | Processors for variable-length-string data |
| . | 18 | The IBM 1401 |
| Section 4 | . | Desk calculator computers: keyboard programmable processors with small memories |
| . | 19 | The OLIVETTI Programma 101 desk calculator |
| . | 20 | The HP Model 9100A computing calculator |
| Section 5 | . | Processors with stack memories (zero addresses per instruction) |
| . | 21 | Design of an arithmetic unit incorporating a nesting store |
| . | 22 | Design of the B 5000 system |
| Section 6 | . | Processors with multiprogramming ability |
| . | 23 | One-level storage system (& the Atlas computer) |
| . | 24 | A user machine in a time-sharing system |
| Part 4 | . | The instruction-set processor level: special-function processors |
| Section 1 | . | Processors to control terminals and secondary memories (input-output processors) |
| . | 25 | The DEC 338 display computer |
| Section 2 | . | Processors for array data |
| . | 26 | NOVA: a list-oriented computer |
| . | 27 | The ILLIAC IV computer |
| Section 3 | . | Processors defined by a microprogram |
| . | 28 | Microprogramming and the design of the control circuits in an electronic digital computer |
| . | 29 | The design of a general-purpose microprogram-controlled computer with elementary structure |
| Section 4 | . | Processors based on a programming language |
| . | 30 | A command structure for complex information processing |
| . | 31 | System design of a FORTRAN machine |
| . | 32 | A microprogrammed implementation of EULER on IBM System/360 Model 30 |
| Part 5 | . | The PMS level |
| Section 1 | . | Computers with one central processor |
| Section 2 | . | Computers with one central processor and multiple input/output processors |
| . | 33 | The IBM 1800 |
| . | 34 | The engineering design of the Stretch computer |
| . | 35 | PILOT, the NBS multicomputer system |
| Section 3 | . | Computers for multiprocessing and parallel processing |
| . | 36 | D825-a multiple-computer system for command and control |
| . | 37 | A survey of problems and preliminary results concerning parallel processing and parallel processors |
| Section 4 | . | Network computers and computer networks |
| . | 38 | The RW-400-a new polymorphic data system |
| . | 39 | Parallel operation in the Control Data 6600 |
| . | 40 | Computer network examples |
| Part 6 | . | Computer families |
| Section 1 | . | The IBM 701-7094 II sequence, a family by evolution |
| . | 41 | The IBM 7094 1, II |
| Section 2 | . | The SDS 910-9300 series, a planned family |
| . | 42 | The SDS 910-9300 |
| Section 3 | . | The IBM System/360- a series of planned machines which span a wide performance range |
| . | 43 | The structure of SYSTEM/360 |
| . | 44 | The structure of SYSTEM/360 |